An electroluminescence element (referred to below as EL element) is known as a light emitting element utilizing an electroluminescence (EL) phenomenon. An EL element has a structure in which an EL material which serves as a light emitting material is sandwiched between an anode and a cathode and emits light at a wavelength depending on the type of EL material.
When a certain voltage is applied between the anode and cathode of an EL element, current flows between both and an EL material emits light with luminosity according to the value of the current. Therefore, it is possible to make an EL element emit light at a desired luminosity by controlling the current value supplied to the EL element.
FIG. 10 is a diagram for explaining an outline of an EL display device 13. The EL display device 13 is arranged with two power sources for supplying a current to an EL element. Specifically, a first power source 11 which outputs a high potential and a second power source 12 which outputs a lower potential than the first power source 11 are arranged, and the EL display device 13 is controlled by supplying the potential from the two power sources.
FIG. 11 is a diagram showing a circuit structure of an outline of the EL display device 13. A pixel circuit 14 and drive circuit 15 are arranged within the EL display device 13 and both electrically connected via a first power source line 16, a gate signal (scanning signal) 17 and data signal line 18. The first power source line 16 and second power source line 19 are connected to the first power source 11 and second power source 12 respectively. In this way, the first power source 11 and second power source 12 are electrically connected to the pixel circuit 14 respectively.
The pixel circuit 14 is respectively arranged in a plurality of pixels which form a pixel part (display region) of the EL display device 13 and performs control for making the EL element emit light according to image data. Basically, the pixel circuit 14 includes a first transistor 14a, second transistor 14b, capacitance element 14c and EL element 14d. The first transistor 14a and second transistor 14b typically are formed from thin film transistor (TFT).
The drive circuit 15 is a logic circuit which generates a gate signal or data signal supplied to the pixel circuit 14 and is typically arranged as drive IC (Integrated Circuit). Basically, the drive circuit 15 includes a logic buffer 15a which supplies a gate signal to the gate signal line 17 and an analog buffer 15b which supplies a data signal to the data signal line 18.
In the EL display device 13 shown in FIG. 11, the first power source 11 is connected to the logic buffer 15a, analog buffer 15b, capacitance element 14c and the source of the second transistor 14b via the first power source line 16. The second power source 12 is connected to a cathode terminal of the EL element 14d via the second power source line 19. In addition, the logic buffer 15a is connected to a gate terminal of the first transistor 14a via the gate signal line 17, and the analog buffer 15b is connected to a source/drain terminal of the first transistor 14a via the data signal line 18.
Actually, the pixel circuit 14 is arranged for each of the plurality of pixels arranged in the pixel part of the EL display device 13 and each pixel circuit 14 is connected to a corresponding gate signal line 17 and data signal line 18. The first power source line 16 and second power source line 19 are commonly connected to all of the pixels.
Next, the circuit operation in the EL display device 13 is explained. In the pixel circuit 14, when an active potential (potential for opening the gate of a transistor) is supplied to the gate terminal of the first transistor 14a via the gate signal line 17, the first transistor 14a is switched to an ON state. In this way, a data signal supplied via the data signal line 18 is stored in the capacitance element 14c via the first transistor 14a. 
The potential stored in the capacitance element 14c is also supplied to the gate terminal of the second transistor 16b. The second transistor 14b flows a current (drain current) according to a potential level of a data signal supplied to a gate terminal and supplies the current to the EL element 14d. The EL element 14d emits light at a luminosity according to the value of the current supplied from the second transistor 14b. That is, when a maximum potential is supplied to the gate terminal of the second transistor 14b, the EL element 14d emits light at maximum luminosity and when a minimum potential is supplied to the gate terminal, the EL element 14d does not emit light.
FIG. 12 is a diagram showing the load characteristics of the second transistor 14b and EL element 14d. In FIG. 12, the horizontal axis is the difference (power source voltage) between the first power source 11 and second power source 12, and the vertical axis is the current (drain current) flowing between the source and drain of the second transistor 14b. 
In FIG. 12, the curved line 21 indicates the voltage-current characteristics of the EL element 14d, what is called diode characteristics. The EL element 14d emits light at a luminosity almost proportional to the value of a current flowing through the element. The curved line 22 indicates the relationship between the voltage between the source and drain of the second transistor 14b and a drain current, what is called MOS transistor characteristics. The second transistor 14b is arranged with a characteristic which does not flow a drain current in the case where a gate/source voltage (difference between a source potential and gate potential) is below a certain threshold and flows a drain voltage when it is above a certain threshold.
Here, a method of setting a power source voltage in the EL display device 13 is explained using FIG. 12. First, a desired maximum luminosity in the EL display device 13 is determined and based on this the value of a current flowing to the EL element 14d is determined. As described above, since the value of a current flowing to the EL element 14d and the value of a current flowing to the second transistor 14b are the same, the intersection between the curved line 21 and the curved line 22 is an operating point in the case where a maximum luminosity is obtained. On the other hand, in the case of a minimum luminosity, since the EL element 14d does not flow a current, the intersection point 27 between the curved line 21 and the horizontal axis becomes the operating point in the case where a minimum luminosity is obtained. In addition, the space between the operating point 23 and the operating point 27 becomes an operating point when displaying at an arbitrary gradation.
In order to consecutively display a luminosity from a minimum luminosity through to a maximum luminosity, the operating point 23 for obtaining a maximum luminosity is required to be set within a saturation region of the second transistor 14b, and in order to reduce power consumption to a minimum, usually the operating point 23 when at maximum luminosity is set near a boundary between a saturation region and linear region of the second transistor 14b. In this way, it is possible to set the power source voltage to a minimum and minimize power consumption.
Here, in the case where a user lowers the luminosity of an EL display device, the potential of a data signal is lowered and the potential supplied to the gate terminal of the second transistor 14b is lowered. That is, the gate voltage of the second transistor 14b is lowered. In this case, the relationship between the voltage between the source and drain of the second transistor 14b and the drain current changes to the relationship shown in the curved line 24. Therefore, the operating point of a maximum luminosity changes to the intersection point 25 from the intersection point 23.
Here, the curved line 26 plots the boundary between the saturation region and linear region of the second transistor 14b with respect to the current characteristics (curved line 22, 24 etc) under various gate voltages. As is clear from FIG. 12, while a user uses an EL display device at a low luminosity, since the operating point 25 is misaligned from the boundary between the saturation region and linear region of the second transistor 14b (that is, intersection point between curved line 24 and curved line 26), minimization of power consumption was not achieved.
In addition, in the EL display device 13, since output potential of the first power source 11 and the output potential of the second power source 12 are constant values respectively, in the case where a user lowers luminosity, only a reduction in power equal to the reduction in the value of the current flowing through the EL element 14d is obtained and it could not be said that a sufficient reduction in power consumption was achieved.
In order to deal with such problems, a technology is disclosed in the patent document 1 in which an output potential of a power source connected to the cathode of an EL element is lowered in the case where the gate voltage of a transistor connected in series is lowered with respect to the EL element, and the voltage (CV margin) applied to the EL element is decreased. In this way, in the EL display device described in patent document 1, in addition to the reduction in power due to a decrease in the value of a current flowing through the EL element, a reduction in power consumption is achieved by a reduction in power due to a decrease in a CV margin.